The defense will take place on Thursday 6th April at 14:00 in the Chappe Amphitheater, Claude Chappe building, INSA Lyon.
The presentation will be held in English with slides in English.
Paolo IENNE, EPFL Lausanne
Roselyne CHOTIN-AVOT, UPMC Paris
David THOMAS, Imperial College London
Frédéric PETROT, ENSIMAG, Saint Martin d’Hères
Olivier SENTIEYS, ENSSAT, Lannion
Florent DE DINECHIN, INSA Lyon
The circuit paradigm enables efficient application-specific parallel computations.
FPGAs also enable arithmetic efficiency: a bit is only computed if it is useful to the final result.
To achieve this, FPGA arithmetic shouldn’t be limited to basic arithmetic operations offered by microprocessors.This thesis studies the implementation of coarser operations on FPGAs, in three main directions.New FPGA-specific approaches for evaluating the sine, cosine and the arctangent have been developed.
Each function is tuned for its context and is as versatile and flexible as possible.
Arithmetic efficiency requires error analysis and parameter tuning, and a fine understanding of the algorithms used.
Digital filters are an important family of coarse operators resembling elementary functions: they can be specified at a high level as a transfer function with constraints on the signal/noise ratio, and then be implemented as an arithmetic datapath based on additions and multiplications.
The main result is a method which transforms a high-level specification into a filter in an automated way.
The first step is building an efficient method for computing sums of products by constants.
Based on this, FIR and IIR filter generators are constructed.
For arithmetic operators to achieve maximum performance, context-specific pipelining is required.
Even if the designer’s knowledge is of great help when building and pipelining an arithmetic datapath, this remains complex and error-prone.
A user-directed, automated method for pipelining has been developed.
This thesis provides a generator of high-quality, ready-made operators for coarse computing cores, which brings FPGA-based computing a step closer to mainstream adoption.
The cores are part of an open-ended generator, where functions are described as high-level objects such as mathematical expressions.