Day: 8 November 2019

PhD Defence: “High-level synthesis and arithmetic optimizations”, Yohann Uguen, Chappe Amphitheater, CITI, 13th of November 2019 at 13h30

Title

High-level synthesis and arithmetic optimizations

Abstract

High-level synthesis (HLS) tools offer increased productivity regarding FPGA programming. However, due to their relatively young nature, they still lack many arithmetic optimizations. This thesis proposes safe arithmetic optimizations that should always be applied. These optimizations are simple operator specializations, following the C semantic. Other require to a lift the semantic embedded in high-level input program languages, which are inherited from software programming, for an improved accuracy/cost/performance ratio. To demonstrate this claim, the sum-of-product of floating-point numbers is used as a case study. The sum is performed on a fixed-point format, which is tailored to the application, according to the context in which the operator is instantiated.

In some cases, there is not enough information about the input data to tailor the fixed-point accumulator. The fall-back strategy used in this thesis is to generate an accumulator covering the entire floating-point range. This thesis explores different strategies for implementing such a large accumulator, including new ones. The use of a 2’s complement representation instead of a sign+magnitude is demonstrated to save resources and to reduce the accumulation loop delay.

Based on a tapered precision scheme and an exact accumulator, the posit number systems claims to be a candidate to replace the IEEE floating-point format. A throughout analysis of posit operators is performed, using the same level of hardware optimization as state-of-the-art floating-point operators. Their cost remains much higher that their floating-point counterparts in terms of resource usage and performance.

Finally, this thesis presents a compatibility layer for HLS tools that allows one code to be deployed on multiple tools. This library implements a strongly typed custom size integer type along side a set of optimized custom operators.

 

Jury

  • Philippe Coussy, Professeur des Universités, UBS, Lorient, France : Rapporteur
  • Olivier Sentieys, Professeur des Universités, Univ. Rennes, Inria, IRISA, Rennes : Rapporteur
  • Laure Gonnord, Maître de conférence, Université Lyon 1, France : Examinatrice
  • Frédéric Pétrot, Professeur des Universités, TIMA, Grenoble, France : Examinateur
  • Martin Kumm, Professeur des Universités, Université de Fulda, Allemagne : Examinateur
  • Florent de Dinechin, Professeur des Universités, INSA Lyon, France : Directeur de thèse

CITI seminar – Martin Kumm (University of Applied Sciences Fulda, Germany) – 13/11 at 10:30AM

Title: Design of Optimal Multiplierless FIR Filters

Date and Place: 13 / 11 / 2019 10:30 in TD-C

Speaker: Martin Kumm (University of Applied Sciences Fulda, Germany)

Host: Florent de Dinechin

Abstract:
In this talk we present a novel method for the simultaneous design of digital filters adhering to a given frequency specification and its dedicated (hardware) implementation. Our methods are based on an integer linear programming (ILP) problem and aim to minimize the number of adders used to implement a digital filter. In the first part, an overview is given about the structure of finite impulse response (FIR) filters which typically contain many costly multiplications. As these are usually multiplications by a constant, they can be reduced to additions, subtractions and bit-shifts, leading to a multiplierless realization. A brief overview of state-of-the-art methods for optimizing constant multiplications is presented. In the second part, novel extensions are presented that also consider the frequency specification of the digital filter in the optimization. Compared to previous multiplierless FIR approaches, the methods introduced here ensure adder count optimality. We show the effectiveness by solving established design problems: our results either prove existing heuristics to be optimal or improve their adder count.

Biography:
Martin Kumm is full professor in the faculty of Applied Computer Science at the University of Applied Sciences Fulda in Germany. His research interests are arithmetic circuits and their optimization in the context of reconfigurable systems (FPGAs). http://www.martin-kumm.de/