PhD Defence: “Autonomous Wireless Sensor Network Architecture for Vehicular traffic monitoring at an Intersection”, Domga Komguem, 6th of July 2020 at 10AM

The defense will take place at the University of Yaoundé I and will be available at


Autonomous Wireless Sensor Network Architecture for Vehicular traffic monitoring at an Intersection



In many countries, because of the limited financial budget, the growth of road infrastructures is low compared to the growth of population and the number of vehicles in urban areas. Such a context does not make the task easy for authorities in charge of the management of transportation systems. The introduction of information and communication technologies (ICT) allows to better address these issues. Vehicular traffic management at intersections has an impact on the traffic jam observed in the whole city. In this thesis, our goal is to propose a low-cost, lightweight and autonomous Wireless Sensors Network (WSN) architecture for vehicular traffic monitoring, especially at an intersection. Vehicular traffic data collected can be used, for instance, for intelligent traffic lights management. In the WSN architecture proposed in the literature for vehicular traffic monitoring, underground sensors are used. In terms of network communication, these architectures are not realistic. Nowadays, surface-mounted sensors are proposed by manufacturers.

The first contribution of this thesis is an experimental characterization of wireless links in a WSN with sensors deployed at the ground level. We evaluate the impact of several parameters like the proximity of the ground surface, the communication frequency and the message size on the link quality. Results show a poor link quality at ground level. Based on the conclusions of the experiments, the second contribution of this thesis is WARIM, a new WSN architecture for vehicular traffic monitoring at an intersection. In WARIM, the sensors deployed on a lane form a multi-hop WSN with a linear topology (LWSN). In this network, all the data are forwarded toward the sink. In a network with such properties, the computation and communication requirements are highest in the neighborhood of the sink. Thus, the third contribution of this thesis is a virtual nodes-based and energy efficient sensors deployment strategy for LWSN. Compared to a uniform deployment, this deployment improves the network lifetime by 40%. In our intersection monitoring application, it is important to correlate the messages generated by a sensor to its position with respect to the intersection. Therefore,the fourth contribution of this thesis is, a centroid-based algorithm for sensors ranking in a LWSN. We evaluate the performance of this algorithm considering a realistic channel model, a uniform deployment, as well as the virtual nodes based-deployment proposed in this thesis. Finally, putting all our contributions together, simulations show that WARIM can be used for reliable and real-time vehicular traffic monitoring at an intersection.



  • Marcel FOUDA, Professor, Université de Yaoundé I, President
  • Thomas DJOTIO, Associate Professor, Université de Yaoundé I, Reviewer
  • Nathalie MITTON, Research Director, INRIA, Reviewer
  • Bernard TOURANCHEAU, Professor, Université Grenoble Alpes, Reviewer
  • André-Luc BEYLOT, Professor, ENSEEIHT Toulouse, Examinator
  • René NDOUNDAM, Associate Professor, Université de Yaoundé I, Examinator
  • Razvan STANICA, HDR, INSA Lyon, Examinator
  • Maurice TCHUENTE, Professor, Université de Yaoundé I, Co-Supervisor
  • Fabrice VALOIS, Professor, INSA Lyon, Co-Supervisor

CITI seminar – Xavier BULTEL (INSA CVL) – 30/01 at 11:00

Title: Sécurité des protocoles de jeux de levées : comment jouer au Bridge avec des tricheurs.

Date and Place: 30 / 01 / 2020 11:00 in TD-C

Speaker: Xavier Bultel (INSA CVL)

Host: Privatics

Les jeux de levées sont des jeux de cartes où chacun des joueurs pose une carte à tour de rôle en fonction d’une règle donnée. Le joueur qui a posé la carte la plus forte gagne la levée, c’est-à-dire toutes les cartes jouées durant la manche. Par exemple, Atout Pique est un jeu de levée très populaire sur les sites de casino en ligne, où chacun des joueurs doit, s’il le peut, jouer une carte de la même couleur que celle de la première carte de la manche. Dans ce genre de jeux, un joueur malhonnête peut jouer une mauvaise carte même s’il à des cartes de la bonne couleur. Comme les autres cartes sont cachées, il est impossible de détecter la triche. Les autres joueurs s’en rendront compte plus tard, lorsque le tricheur jouera une carte qu’il n’est pas sensé avoir. Dans ce cas, le jeu est biaisé et doit être annulé, et l’équipe qui a triché se voit attribuer une pénalité de paiement. cela pose problème si le partenaire du tricheur n’est pas son complice, ce qui est le cas dans les jeux en ligne puisque les joueurs sont appareillés par le serveur du site. Notre but est de proposer un protocole cryptographique qui prévient ce genre de triche. Dans ce tte présentation on définit d’abord un modèle de sécurité pour les protocoles d’Atout Pique sécurisés, puis on construit un protocole appelé SecureSpades. Ce protocole est prouvé sûr dans notre modèle sous l’hypothèse Diffie-Hellman Décisionnel, dans le modèle de l’oracle aléatoire. Notre modèle de sécurité et notre protocole peuvent être étendus à un grand nombre d’autres jeux de levées, comme la Belotte, le Bridge, le Whist, etc.

Xavier Bultel, MdC à l’INSA CVL depuis septembre 2019 ; Ex Postdoc à l’IRISA à Rennes (2018-2019) et doctorant au LIMOS à Clermont-Ferrand sous la direction de Pascal Lafourcade (2014-2018).

CITI seminar – Julien Bourgeois (Univ. Bourgogne-Franche-Comté, Institut FEMTO-ST, CNRS) – 23/01 at 14:00

Title: Building programmable matter with micro-robots

Date and Place: 23 / 01 / 2020 14:00 in TD-C

Speaker: Julien Bourgeois (Univ. Bourgogne-Franche-Comté, Institut FEMTO-ST, CNRS)

Host: Olivier Simonin

Technological advances, especially in the miniaturization of robotic devices foreshadow the emergence of large-scale ensembles of small-size resource-constrained robots that distributively cooperate to achieve complex tasks. These ensembles are formed by independent, intelligent and communicating units which act as a whole ensemble which can be used to build programmable matter i.e. matter able to change its shape.
In my talk, I will present our research effort in building Programmable Matter (PM) based on modular robots. To do this, we use micro-technology to scale down the size of each element, and we study geometry, structure, actuation, power, electronics and integration. To manage the complexity of this kind of environment, we propose a complete environment including programmable hardware, a programming language, a compiler, a simulator, a debugger and distributed algorithms.

Julien Bourgeois is a professor of computer science at the University of Bourgogne Franche-Comté (UBFC) in France. He is leading the computer science department at the FEMTO-ST institute/CNRS. His research interests include distributed intelligent MEMS (DiMEMS), Programmable Matter, P2P networks and security management for complex networks. He has worked for more than 15 years on these topics and has co-authored more than 160 international publications. He was an invited professor at Carnegie Mellon University (US) from 2012 to 2013, at Emory University (US) in 2011 and at Hong Kong Polytechnic University in 2010, 2011 and 2015. He led different funded research projects (Smart Surface, Smart Blocks, Computation and coordination for DiMEMS). He is currently leading the programmable matter project funded by the ANR and the ISITE-BFC project. He organized and chaired many conferences (dMEMS 2010, 2012, HotP2P/IPDPS 2010, Euromicro PDP 2008 and 2010, IEEE GreenCom 2012, IEEE iThings 2012, IEEE CPSCom 2012, GPC 2012, IEEE HPCC 2014, IEEE ICESS 2014, CSS 2014, IEEE CSE 2016, IEEE EUC 2015, IEEE ATC 2017, IEEE CBDCom 2017).


PhD Defence: “Dynamic Heterogeneous Memory Allocation for embedded devices”, Tristan Delizy, Chappe Amphitheater, CITI, 19th of December 2019 at 10h00


Dynamic Heterogeneous Memory Allocation for embedded devices


Reducing energy consumption is a key challenge to the realisation of the Internet of Things. While emerging memory technologies may offer power reduction and high integration density, they come with major drawbacks such as high latency or limited endurance. As a result, system designers tend to juxtapose several memory technologies on the same chip. We aim to provide the embedded application programmer with a transparent software mechanism to leverage this memory heterogeneity. This work studies the interaction between dynamic memory allocation and memory heterogeneity. We provide cycle accurate simulation of embedded platforms with various memory technologies and we show that different dynamic allocation strategies have a major impact on performance. We demonstrates that interesting performance gains can be achieved even for a low fraction of memory using low latency technology, but only with a clever placement strategy between memory banks. We propose an efficient strategy based on application profiling in our simulator.



  • Olivier Sentieys, Professeur des Universités, Université de Rennes – Examinateur
  • Cécile Belleudy, Maitre de Conférence HDR, Université de Nice Sophia Antipolis – Rapporteure
  • Lionel Torres, Professeur des Universités, Université de Montpellier – Rapporteur
  • Guillaume Salagnac, Maitre de Conférences, INSA de Lyon – Examinateur, Encadrant
  • Tanguy Risset, Professeur des Universités, INSA de Lyon – Examinateur, Co-directeur de thèse
  • Matthieu Moy, Maitre de Conférences HDR, Université Claude Bernard Lyon 1 – Examinateur, Co-directeur de thèse

Journées Nationales de la Recherche en Robotique

Du 14 au 17 octobre, Olivier Simonin a co-présidé avec François Charpillet (Inria Nancy) les JNRR 2019 Journées Nationales de la Recherche en Robotique, qui se sont tenues à Vittel et parrainées par le GDR Robotique. Le 13 octobre était également organisée la Journée des Jeunes Chercheurs en Robotique JJCR, et les 17/18 un tutoriel Apprentissage & Robotique était organisé par Christian Wolf et David Filliat.

L’événement, qui a lieu tous les 2 ans, a eu un fort succès en accueillant 200 participants, qui ont pu suivre 27 exposés scientifiques sur 3 jours.

Site des JNRR 2019 (accès au programme) :

CITI seminar – John Manuel Delgado and Michael Puentes (TInteresaLab de Unidades Tecnológicas de Santander) – 22/11 at 9:00AM

Title: Pedestrian Behavior Modeling and Simulation from Real Time Data Information

Date and Place: 22 / 11 / 2019 09:00 in TD-D

Speaker: John Manuel Delgado and Michael Puentes (TInteresaLab de Unidades Tecnológicas de Santander – UTS, Colombia)

Host: Oscar Carrillo

Accidents of pedestrians sometimes take lives, in Bucaramanga since 2012 pedestrian died by accidents are 179, and 2873 hurt, In a city like Bucaramanga-Colombia, this means each day at least one pedestrian is involved in an accident. Therefore is necessary to know the causes of accidents in the way to decrease the accidents. One of many reasons to know the causes is with system dynamics, simulating the events of the Pedestrian behavior when accidents occur in risen cities. The implementation simulation joint with technology and research looking for saving lives, reducing the accidental rate, and to implementing or suggesting new policies from the government. This project is looking for the implementation of technology in video records and Deep Learning analysis for the service of the citizens, where a simulation model will be revealing the main variables which intervene in the pedestrian’s behavior. As initials results, shows the methodology here implemented, can reach data which was insufficient before thanks to the cameras and software of objects detection, those are the data input for the simulation model, which after to implement a change in a particular spot of Bucaramanga is possible to decrease the accident rate in 80% where pedestrians could be involved.


PhD Defence: “High-level synthesis and arithmetic optimizations”, Yohann Uguen, Chappe Amphitheater, CITI, 13th of November 2019 at 13h30


High-level synthesis and arithmetic optimizations


High-level synthesis (HLS) tools offer increased productivity regarding FPGA programming. However, due to their relatively young nature, they still lack many arithmetic optimizations. This thesis proposes safe arithmetic optimizations that should always be applied. These optimizations are simple operator specializations, following the C semantic. Other require to a lift the semantic embedded in high-level input program languages, which are inherited from software programming, for an improved accuracy/cost/performance ratio. To demonstrate this claim, the sum-of-product of floating-point numbers is used as a case study. The sum is performed on a fixed-point format, which is tailored to the application, according to the context in which the operator is instantiated.

In some cases, there is not enough information about the input data to tailor the fixed-point accumulator. The fall-back strategy used in this thesis is to generate an accumulator covering the entire floating-point range. This thesis explores different strategies for implementing such a large accumulator, including new ones. The use of a 2’s complement representation instead of a sign+magnitude is demonstrated to save resources and to reduce the accumulation loop delay.

Based on a tapered precision scheme and an exact accumulator, the posit number systems claims to be a candidate to replace the IEEE floating-point format. A throughout analysis of posit operators is performed, using the same level of hardware optimization as state-of-the-art floating-point operators. Their cost remains much higher that their floating-point counterparts in terms of resource usage and performance.

Finally, this thesis presents a compatibility layer for HLS tools that allows one code to be deployed on multiple tools. This library implements a strongly typed custom size integer type along side a set of optimized custom operators.



  • Philippe Coussy, Professeur des Universités, UBS, Lorient, France : Rapporteur
  • Olivier Sentieys, Professeur des Universités, Univ. Rennes, Inria, IRISA, Rennes : Rapporteur
  • Laure Gonnord, Maître de conférence, Université Lyon 1, France : Examinatrice
  • Frédéric Pétrot, Professeur des Universités, TIMA, Grenoble, France : Examinateur
  • Martin Kumm, Professeur des Universités, Université de Fulda, Allemagne : Examinateur
  • Florent de Dinechin, Professeur des Universités, INSA Lyon, France : Directeur de thèse

CITI seminar – Martin Kumm (University of Applied Sciences Fulda, Germany) – 13/11 at 10:30AM

Title: Design of Optimal Multiplierless FIR Filters

Date and Place: 13 / 11 / 2019 10:30 in TD-C

Speaker: Martin Kumm (University of Applied Sciences Fulda, Germany)

Host: Florent de Dinechin

In this talk we present a novel method for the simultaneous design of digital filters adhering to a given frequency specification and its dedicated (hardware) implementation. Our methods are based on an integer linear programming (ILP) problem and aim to minimize the number of adders used to implement a digital filter. In the first part, an overview is given about the structure of finite impulse response (FIR) filters which typically contain many costly multiplications. As these are usually multiplications by a constant, they can be reduced to additions, subtractions and bit-shifts, leading to a multiplierless realization. A brief overview of state-of-the-art methods for optimizing constant multiplications is presented. In the second part, novel extensions are presented that also consider the frequency specification of the digital filter in the optimization. Compared to previous multiplierless FIR approaches, the methods introduced here ensure adder count optimality. We show the effectiveness by solving established design problems: our results either prove existing heuristics to be optimal or improve their adder count.

Martin Kumm is full professor in the faculty of Applied Computer Science at the University of Applied Sciences Fulda in Germany. His research interests are arithmetic circuits and their optimization in the context of reconfigurable systems (FPGAs).

CITI Seminar of Erwan Le Merrer / Gilles Tredan (Inria-Rennes / LAAS-CNRS) on October 9 at 3pm

Title: The Bouncer Problem: Challenges to Remote Explainability

Date and Place: 09 / 10 / 2019 3PM in 432 (Antenne Inria)

Host: Privatics

The concept of explainability is envisioned to satisfy society’s demands for transparency on machine learning decisions. The concept is simple: like humans, algorithms should explain the rationale behind their decisions so that their fairness can be assessed. While this approach is promising in a local context (e.g. to explain a model during debugging at training time), we argue that this reasoning cannot simply be transposed in a remote context, where a trained model by a service provider is only accessible through its API. This is problematic as it constitutes precisely the target use-case requiring transparency from a societal perspective. Through an analogy with a club bouncer (which may provide untruthful explanations upon customer reject), we show that providing explanations cannot prevent a remote service from lying about the true reasons leading to its decisions.

More precisely, we prove the impossibility of remote explainability for single explanations, by constructing an attack on explanations that hides discriminatory features to the querying user. We provide an example implementation of this attack. We then show that the probability that an observer spots the attack, using several explanations for attempting to find incoherences, is low in practical settings. This undermines the very concept of remote explainability in general.

Erwan is on an “advanced research position” at Inria, in the WIDE team, since Nov. 2018. He was previously senior research scientist at Technicolor R&I (2009-2018). Gilles is a “chargé de recherches” at CNRS since 2011.

CITI Seminar of Subhash Lakshminarayana (University of Warwick’s School of Engineering) on September 19 at 2pm

Title: On False Data Injection Attacks Against Power Grids and Countermeasures

Date and Place: 19 / 09 / 2019 2PM in TD-C

Host: Samir M. Perlaza

The power grid state estimation (SE) has been shown to be vulnerable to false data injection (FDI) attacks, which can lead to severe consequences, e.g., transmission line trips, unsafe frequency excursions and/or economic losses. In this talk, we will examine the security of power gird SE from both the attacker and the defender’s perspective. For the former, we examine data-driven FDI attacks, i.e., constructing FDI attacks that can bypass the grid’s bad-data detector (BDD) by accessing its measurement data over a period of time. We characterize important tradeoffs for the attacker in this context between the attack’s spatial and temporal efficiency. The results provide us with an understanding for designing defense mechanism to thwart such attacks. For defense, we propose a hardened-attack detector based on moving-target defense (MTD) that actively perturbs transmission line reactances to invalidate the attacker’s knowledge. We present novel formal design criteria to select MTD reactance perturbations that are truly effective. Moreover, based on a key optimal power flow formulation, we find that the effective MTD may incur a non-trivial operational cost. Accordingly, we characterize important tradeoffs between the MTD’s detection capability and its associated required cost. Extensive simulations, using the MATPOWER simulator and benchmark IEEE bus systems, verify and illustrate the proposed design approach.

Subhash Lakshminarayana is an assistant professor in the University of Warwick’s School of Engineering since September 2018. Prior to joining Warwick, he worked as a research scientist at the Advanced Digital Sciences Center (ADSC) in Singapore between 2015-2018. Before that, he held joint post-doctoral researcher appointment at Princeton University and the Singapore University of Technology and Design (SUTD) between 2013-2015. He received his PhD in the field of Wireless Communications at the Department of Telecommunications at Ecole Superieure d’Electricite (Supelec) Paris, France, M.S. degree from The Ohio State University, USA and B.S. from Bangalore University in India. His research interests include cyber-physical system security (power grids and urban transportation) and wireless communications. His works have been selected among the Best Conference Papers at the IEEE Power Energy Society General Meeting (PESGM) 2015 conference, and the Best 50 Papers at the IEEE Globecom 2014 conference.